모집부문 및 자격요건

근무조건 및 환경

전형절차 및 제출서류

접수기간 및 방법

담당업무 & 지원 요건

Job description:

The primary focus of this Verification Applications Consultant is to support the sales activities and adoption of the Synopsys Verification solution - VCS, Verdi debug platform, Verification IP (VIP), Static Verification and System Verilog/UVM Test bench methodology.

As a Verification AC, the candidate will be driving the effort to enable the verification methodology and solution for customers using Synopsys Verification tools.

This specialist is expected to possess in-depth knowledge of RTL simulation and System Verilog/UVM test bench development with strong debugging skills.

In this role, he/she will work directly with customers to assist with the evaluation and the deployment of the verification methodologies, resolve any technical issues and provide required training.
The responsibilities include pre-sales & post-sales support such as product demonstrations, evaluations, and competitive benchmarking. He/She will participate in the account planning and work with the sales team to develop the account strategy and expand Synopsys Verification market.
 
Job Requirements:

BS in CS/EE with 8+ years of experience, or MS in CS/EE with at least 5 years of experience.

Strong knowledge of SystemVerilog/UVM, Verilog and VHDL

Strong knowledge of digital logic simulation and debugging techniques

Minimum 5+ years of experience with Block Level and SOC Level verification is a requirement

Experience on Low Power verification with UPF or Static Verification tools is a plus. (Formal verification, Lint, etc)

Sharp debugging skills on designs and SystemVerilog/UVM environment is mandatory

Critical thinking and problem solving skills are required

English written and verbal communication skill

Excellent presentation/communication skills and strong organization skills

Self-management and scheduling is preferred